8-267 40,000 usable pld gate pasic 3 fpga combining high performance and high density ql3040 - pasic 3 fpga tm ql3040 rev d ql3040 - pasic 3 fpga device highlights device highlights high performance & high density 40,000 usable pld gates with 252 i/os 16-bit counter speeds over 300 mhz, data path speeds over 400 mhz 0.35um four-layer metal non-volatile cmos process for smallest die sizes easy to use / fast development cycles 100% routable with 100% utilization and complete pin-out stability variable-grain logic cells provide high performance and 100% utilization comprehensive design tools include high quality verilog/vhdl synthesis advanced i/o capabilites interfaces with both 3.3v and 5.0v devices pci compliant with 3.3v and 5.0v buses for -1/-2/-3/-4 speed grades full jtag boundary scan registered i/o cells with individually controlled clocks and output enables total of 252 i/o pins 244 bidirectional input/output pins, pci-compliant for 5.0v and 3.3v buses for -1/-2/-3/-4 speed grades 8 high-drive input/distributed network pins eight low-skew distributed networks two array clock/control networks available to the logic cell flip- flop clock, set and reset inputs - each driven by an input-only pin six global clock/control networks available to the logic cell f1, clock set and reset inputs and the input and i/o register clock, reset and enable inputs as well as the output enable control - each driven by an input-only or i/o pin, or any logic cell output or i/o cell feedback high performance input + logic cell + output total delays under 6 ns data path speeds over 400 mhz counter speeds over 300 mhz d evice h ighlights figure 1. 1,008 logic cells product summary the ql3040 is a 40,000 usable pld gate member of the pasic 3 family of fpgas. pasic 3 fpgas are fabricated on a 0.35mm four-layer metal process using quicklogic?s patented vialink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. the ql3040 contains 1,008 logic cells. with a maximum of 252 i/os, the ql3040 is available in 208-pqfp and 456-pin pbga packages. software support for the complete pasic 3 family, including the ql3040, is available through three basic packages. the turnkey quickworks ? package provides the most complete fpga software solution from design entry to logic synthesis, to place and route, to simulation. the quickchiptm and quicktoolstm packages provide a solution for designers who use cadence, exemplar, mentor, synopsys, synplicity, viewlogic, veribest, or other third-party tools for design entry, synthesis, or simulation. p roduct s ummary
268 preliminary 8-268 ql3040 - pasic 3 fpga tm 208-pin pqfp pinout diagrams figure 2. 208-pin pqfp p asic p inout d iagram 208-p in pqfp p inout d iagram ql3040-1pq208c pasic pin #1 pin #53 pi n #157 pin #105
8-269 ql3040 - pasic 3 fpga tm 208 pqfp pinout table 208 pqfp function 208 pqfp function 208 pqfp function 208 pqfp function 208 pqfp function 208 i/o 43 gnd 84 i/o 125 i/o 168 i/o 1 i/o 44 i/o 85 i/o 126 i/o 169 i/o 2 i/o 45 i/o 86 i/o 127 gnd nc i/o 3 i/o 46 i/o 87 i/o 128 i/o 170 i/o 4 i/o 47 i/o 88 i/o nc i/o 171 i/o 5 i/o 48 i/o 89 i/o 129 gclk/i 172 i/o nc i/o nc i/o 90 i/o 130 aclk/i 173 i/o 6 i/o 49 i/o 91 i/o 131 vcc 174 i/o 7 i/o 50 i/o 92 i/o 132 gclk/i 175 i/o 8 i/o 51 i/o nc i/o 133 gclk/i nc i/o 9 i/o 52 i/o 93 i/o 134 vcc 176 i/o 10 vcc 53 i/o 94 i/o 135 i/o 177 gnd 11 i/o 54 tdi 95 gnd 136 i/o 178 i/o 12 gnd nc i/o 96 i/o nc i/o 179 i/o 13 i/o nc i/o 97 vcc 137 i/o nc i/o 14 i/o 55 i/o 98 i/o nc gnd 180 i/o nc i/o 56 i/o 99 i/o 138 i/o 181 i/o 15 i/o nc i/o 100 i/o 139 i/o 182 gnd 16 i/o 57 i/o nc i/o 140 i/o nc vcc 17 i/o 58 i/o 101 i/o 141 i/o 183 i/o 18 i/o 59 gnd nc i/o 142 i/o 184 i/o 19 i/o 60 i/o 102 i/o nc i/o 185 i/o 20 i/o 61 vcc nc i/o 143 i/o 186 i/o nc i/o 62 i/o nc i/o 144 i/o 187 vccio 21 i/o 63 i/o 103 trstb 145 vcc 188 i/o 22 i/o 64 i/o 104 tms nc i/o nc i/o 23 gnd nc i/o 105 i/o 146 i/o 189 i/o 24 i/o 65 i/o nc i/o 147 gnd 190 i/o 25 gclk/i 66 i/o 106 i/o 148 i/o 191 i/o 26 gclk/i 67 i/o 107 i/o 149 i/o 192 i/o 27 vcc nc i/o 108 i/o 150 i/o 193 i/o 28 gclk/i 68 i/o 109 i/o 151 i/o 194 i/o 29 gclk/i 69 i/o nc i/o 152 i/o nc i/o 30 vcc 70 i/o 110 i/o 153 i/o 195 i/o 31 i/o nc i/o 111 i/o 154 i/o 196 i/o 32 i/o 71 i/o 112 i/o 155 i/o 197 i/o nc gnd nc i/o 113 i/o 156 i/o 198 i/o 33 i/o 72 i/o 114 vcc 157 tck nc i/o nc i/o 73 gnd 115 i/o 158 stm 199 gnd 34 i/o 74 i/o 116 gnd nc i/o 200 i/o 35 i/o nc vcc 117 i/o 159 i/o 201 vcc 36 i/o 75 i/o nc i/o 160 i/o 202 i/o nc i/o 76 i/o 118 i/o 161 i/o 203 i/o 37 i/o 77 i/o 119 i/o 162 i/o 204 i/o 38 i/o 78 gnd 120 i/o 163 gnd 205 i/o 39 i/o 79 i/o 121 i/o 164 i/o 206 i/o nc i/o 80 i/o nc i/o 165 vcc 207 tdo 40 i/o 81 i/o 122 i/o 166 i/o 41 vcc 82 i/o 123 i/o nc i/o 42 i/o 83 vccio 124 i/o 167 i/o 208 pqfp p inout t able
270 preliminary 8-270 ql3040 - pasic 3 fpga tm 456-pin pbga pinout diagram top bottom 456-p in pbga p inout d iagram ql3040-1pb456c pasic a b c d e f g h j k l m n p r t u v w y 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 pin a1 corner
8-271 ql3040 - pasic 3 fpga tm pbga 456 pinout table pbga 456 p inout t able 456 function 456 function 456 function 456 function 456 function a1 i/o b26 stm d25 i/o h4 i/o m14 gnd/therm a2 i/o c1 i/o d26 i/o h5 nc m15 gnd/therm a3 i/o c2 i/o e1 i/o h22 nc m16 gnd/therm a4 i/o c3 i/o e2 i/o h23 nc m22 nc a5 i/o c4 tdo e3 i/o h24 i/o m23 nc a6 i/o c5 i/o e4 i/o h25 nc m24 i/o a7 i/o c6 i/o e5 gnd h26 i/o m25 i/o a8 i/o c7 i/o e6 vcc j1 i/o m26 i/o a9 nc c8 i/o e7 gnd j2 i/o n1 gclk/i a10 i/o c9 i/o e8 nc j3 i/o n2 i/o a11 i/o c10 i/o e9 gnd j4 nc n3 i/o a12 vccio c11 i/o e10 i/o j5 gnd n4 gclk/i a13 i/o c12 i/o e11 gnd j22 nc n5 vcc a14 i/o c13 i/o e12 gnd j23 nc n11 gnd/therm a15 nc c14 i/o e13 vcc j24 i/o n12 gnd/therm a16 i/o c15 i/o e14 gnd j25 i/o n13 gnd/therm a17 nc c16 i/o e15 gnd j26 i/o n14 gnd/therm a18 i/o c17 nc e16 gnd k1 nc n15 gnd/therm a19 i/o c18 nc e17 nc k2 nc n16 gnd/therm a20 i/o c19 i/o e18 gnd k3 i/o n22 gnd a21 nc c20 i/o e19 nc k4 i/o n23 i/o a22 i/o c21 i/o e20 gnd k5 vcc n24 i/o a23 nc c22 i/o e21 vcc k22 gnd n25 nc a24 i/o c23 i/o e22 gnd k23 i/o n26 i/o a25 i/o c24 i/o e23 i/o k24 i/o p1 i/o a26 i/o c25 tck e24 i/o k25 nc p2 i/o b1 i/o c26 nc e25 i/o k26 i/o p3 nc b2 nc d1 i/o e26 i/o l1 i/o p4 i/o b3 i/o d2 i/o f1 i/o l2 i/o p5 nc b4 nc d3 i/o f2 i/o l3 i/o p11 gnd/therm b5 nc d4 gnd f3 nc l4 i/o p12 gnd/therm b6 nc d5 nc f4 nc l5 nc p13 gnd/therm b7 nc d6 nc f5 vcc l11 gnd/therm p14 gnd/therm b8 nc d7 i/o f22 vcc l12 gnd/therm p15 gnd/therm b9 i/o d8 i/o f23 nc l13 gnd/therm p16 gnd/therm b10 nc d9 gnd f24 i/o l14 gnd/therm p22 nc b11 nc d10 i/o f25 i/o l15 gnd/therm p23 gclk / i b12 i/o d11 i/o f26 i/o l16 gnd/therm p24 gclk / i b13 i/o d12 gnd g1 i/o l22 nc p25 nc b14 nc d13 i/o g2 i/o l23 i/o p26 aclk / i b15 i/o d14 i/o g3 i/o l24 i/o r1 nc b16 i/o d15 gnd g4 i/o l25 nc r2 i/o b17 i/o d16 i/o g5 nc l26 i/o r3 i/o b18 i/o d17 i/o g22 gnd m1 aclk / i r4 nc b19 i/o d18 gnd g23 nc m2 gclk/i r5 nc b20 i/o d19 i/o g24 i/o m3 i/o r11 gnd/therm b21 i/o d20 nc g25 i/o m4 nc r12 gnd/therm b22 i/o d21 nc g26 i/o m5 gnd r13 gnd/therm b23 nc d22 i/o h1 nc m11 gnd/therm r14 gnd/therm b24 i/o d23 gnd h2 i/o m12 gnd/therm r15 gnd/therm b25 i/o d24 i/o h3 nc m13 gnd/therm r16 gnd/therm (continued next page)
272 preliminary 8-272 ql3040 - pasic 3 fpga tm pbga 456 pinout table (continued from previous page) 456 function 456 function 456 function 456 function r22 vcc y1 nc ac6 nc ae5 i/o r23 nc y2 i/o ac7 nc ae6 i/o r24 nc y3 nc ac8 nc ae7 i/o r25 i/o y4 i/o ac9 nc ae8 i/o r26 gclk / i y5 i/o ac10 nc ae9 i/o t1 i/o y22 gnd ac11 i/o ae10 i/o t2 i/o y23 i/o ac12 nc ae11 i/o t3 i/o y24 nc ac13 i/o ae12 i/o t4 i/o y25 i/o ac14 vccio ae13 i/o t5 vcc y26 i/o ac15 nc ae14 i/o t11 gnd/therm aa1 i/o ac16 nc ae15 i/o t12 gnd/therm aa2 i/o ac17 nc ae16 i/o t13 gnd/therm aa3 nc ac18 nc ae17 i/o t14 gnd/therm aa4 nc ac19 i/o ae18 i/o t15 gnd/therm aa5 vcc ac20 i/o ae19 i/o t16 gnd/therm aa22 vcc ac21 i/o ae20 i/o t22 gnd aa23 nc ac22 nc ae21 i/o t23 i/o aa24 i/o ac23 gnd ae22 nc t24 i/o aa25 i/o ac24 nc ae23 nc t25 nc aa26 i/o ac25 i/o ae24 tms t26 i/o ab1 nc ac26 i/o ae25 i/o u1 nc ab2 i/o ad1 i/o ae26 i/o u2 i/o ab3 i/o ad2 nc af1 i/o u3 i/o ab4 i/o ad3 i/o af2 nc u4 i/o ab5 gnd ad4 i/o af3 i/o u5 gnd ab6 vcc ad5 i/o af4 nc u22 nc ab7 nc ad6 i/o af5 i/o u23 i/o ab8 nc ad7 i/o af6 i/o u24 i/o ab9 nc ad8 i/o af7 i/o u25 i/o ab10 vcc ad9 nc af8 i/o u26 i/o ab11 gnd ad10 i/o af9 i/o v1 i/o ab12 nc ad11 nc af10 i/o v2 i/o ab13 i/o ad12 i/o af11 nc v3 nc ab14 gnd ad13 i/o af12 i/o v4 nc ab15 vcc ad14 i/o af13 i/o v5 nc ab16 i/o ad15 i/o af14 nc v22 gnd ab17 nc ad16 i/o af15 nc v23 nc ab18 vcc ad17 i/o af16 i/o v24 i/o ab19 gnd ad18 i/o af17 i/o v25 nc ab20 nc ad19 nc af18 i/o v26 i/o ab21 vcc ad20 nc af19 nc w1 i/o ab22 gnd ad21 i/o af20 i/o w2 i/o ab23 i/o ad22 i/o af21 i/o w3 i/o ab24 nc ad23 trstb af22 i/o w4 i/o ab25 i/o ad24 nc af23 i/o w5 nc ab26 i/o ad25 i/o af24 i/o w22 nc ac1 i/o ad26 i/o af25 i/o w23 i/o ac2 i/o ae1 tdi af26 i/o w24 i/o ac3 nc ae2 i/o w25 i/o ac4 gnd ae3 i/o w26 nc ac5 nc ae4 i/o note: nc pins must be left unconnected on printed circuit board.
8-273 ql3040 - pasic 3 fpga tm pin descriptions pin descriptions ordering information p in d escriptions pin function description tdi test data in for jtag hold high during normal operation. connect to vcc if not used for jtag. trstb active low reset for jtag hold low during normal operation. connect to ground if not used for jtag. tms test mode select for jtag hold high during normal operation. connect to vcc if not used for jtag. tck test clock for jtag hold high or low during normal operation. connect to vcc or ground if not used for jtag. tdo test data out for jtag output that must be left unconnected if not used for jtag. stm special test mode must be grounded during normal operation. i/aclk high-drive input and/or array network driver can be configured as either or both. i/gclk high-drive input and/or global network driver can be configured as either or both. i high-drive input use for input signals with high fanout. i/o input/output pin can be configured as an input and/or output. vcc power supply pin connect to 3.3v supply. vccio input voltage tolerance pin connect to 5.0 volt supply if 5 volt input tolerance is required, otherwise connect to 3.3v supply. gnd ground pin connect to ground. ql 3040 - 1 pq208 c operating range c = commercial i = industrial *m = military package code pq208 = 208-pin pqfp p b456 = 456-pin pbga * contact quicklogic regarding availability. quicklogic pasic device pasic 3 device part number speed grade 0 = quick 1 = fast 2 = faster 3 = faster *4 = fastest
274 preliminary 8-274 ql3040 - pasic 3 fpga tm absolute maximum ratings vcc voltage . . . . . . . . . . . . . . . . . . . -0.5 to 4.6v vccio voltage . . . . . . . . . . . . . . . . . -0.5 to 7.0v input voltage . . . . . . . . . . . . -0.5 to vccio +0.5v latch-up immunity . . . . . . . . . . . . . . . . . 200 ma dc input current . . . . . . . . . . . . . . . . . . . 20 ma esd pad protection . . . . . . . . . . . . . . . . . 2000v storage temperature . . . . . . . . . -65 c to +150 c lead temperature . . . . . . . . . . . . . . . . . . . 300 c operating range dc characteristics notes: [1] applies only to -1/-2/-3/-4 commercial grade devices. these speed grades are also pci-compliant. all other devices have 8 ma iol specifications. [2] capacitance is sample tested only. clock pins are 12 pf maximum. [3] only one output at a time. duration should not exceed 30 seconds. [4] for -1/-2/-3/-4 commercial grade devices only. maximum icc is 3 ma for -0 commercial grade and all industrial grade devices, and 5 ma for all military grade devices. for ac conditions, contact quicklogic customer engineering. symbol parameter military industrial commercial unit min max min max min max vcc supply voltage 3.0 3.6 3.0 3.6 3.0 3.6 v vccio i/o input tolerance voltage 3.0 5.5 3.0 5.5 3.0 5.25 v ta ambient temperature -55 -40 85 0 70 c tc case temperature 125 c -0 speed grade 0.43 1.90 0.46 1.85 k delay factor -1 speed grade 0.42 1.64 0.43 1.54 0.46 1.50 -2 speed grade 0.42 1.37 0.43 1.28 0.46 1.25 -3 speed grade n/a n/a 0.43 0.90 0.46 0.88 -4 speed grade n/a n/a 0.43 0.82 0.46 0.80 symbol parameter conditions min max unit vih input high voltage 0.5vcc vccio+0.5 v vil input low voltage -0.5 0.3vcc v voh output high voltage ioh = -12 ma 2.4 v ioh = -500 a 0.9vcc v vol output low voltage iol = 16 ma [1] 0.45 v iol = 1.5 ma 0.1vcc v ii i or i/o input leakage current vi = vccio or gnd -10 10 a ioz 3-state output leakage current vi = vccio or gnd -10 10 a ci input capacitance [2] 10 pf ios output short circuit current [3] vo = gnd -15 -180 ma vo = vcc 40 210 ma icc d.c. supply current [4] vi, vio = vccio or gnd 0.50 (typ) 2 ma iccio d.c. supply current on vccio 0 100 a
8-275 ql3040 - pasic 3 fpga tm ac characteristics at vcc = 3.3v, ta = 25 c (k = 1.00) (to calculate delays, multiply the appropriate k factor in the "operating range" section by the following numbers.) logic cells input-only/clock cells notes: [5] stated timing for worst case propagation delay over process variation at vcc=3.3v and ta=25c. multi- ply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. [6] these limits are derived from a representative selection of the slowest paths through the pasic 3 logic cell including typical net delays. worst case delay values for specific paths should be determined from timing analysis of your particular design. symbol parameter propagation delays (ns) fanout [5] 12348 tpd combinatorial delay [6] 1.4 1.7 1.9 2.2 3.2 tsu setup time [6] 1.7 1.7 1.7 1.7 1.7 th hold time 0.0 0.0 0.0 0.0 0.0 tclk clock to q delay 0.7 1.0 1.2 1.5 2.5 tcwhi clock high time 1.2 1.2 1.2 1.2 1.2 tcwlo clock low time 1.2 1.2 1.2 1.2 1.2 tset set delay 1.0 1.3 1.5 1.8 2.8 treset reset delay 0.8 1.1 1.3 1.6 2.6 tsw set width 1.9 1.9 1.9 1.9 1.9 trw reset width 1.8 1.8 1.8 1.8 1.8 symbol parameter propagation delays (ns) fanout [5] 123481224 tin high drive input delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4 tini high drive input, inverting delay 1.6 1.7 1.9 2.0 2.5 3.0 4.5 tisu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 3.1 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 tlclk input register clock to q 0.7 0.8 1.0 1.1 1.6 2.1 3.6 tlrst input register reset delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5 tlesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 2.3 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0
276 preliminary 8-276 ql3040 - pasic 3 fpga tm clock cells i/o cells notes: [7] the array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. the number of half columns used does not affect clock buffer delay. the array clock has up to 8 loads per half column. the global clock has up to 11 loads per half column. [8] the following loads are used for tpxz: symbol parameter propagation delays (ns) loads per half column [7] 123481011 tack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 tgckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 tgckb global clock buffer delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3 symbol parameter propagation delays (ns) fanout [5] 1234810 ti/o input delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6 tisu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 tloclk input register clock to q 0.7 1.0 1.2 1.5 2.5 3.0 tlorst input register reset delay 0.6 0.9 1.1 1.4 2.4 2.9 tlesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 symbol parameter propagation delays (ns) output load capacitance (pf) 30 50 75 100 150 toutlh output delay low to high 2.1 2.5 3.1 3.6 4.7 touthl output delay high to low 2.2 2.6 3.2 3.7 4.8 tpzh output delay tri-state to high 1.2 1.7 2.2 2.8 3.9 tpzl output delay tri-state to low 1.6 2.0 2.6 3.1 4.2 tphz output delay high to tri-state [8] 2.0 tplz output delay low to tri-state [8] 1.2 5 pf 1k ? 5 pf 1k ? tphz tplz
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